Microelectronic devices are fabricated on a semiconductor substrate as integrated circuits in which various conductive layers are interconnected with one another to permit electronic signals to propagate within the device. An example of such a device is a complementary metal-oxide-semiconductor (CMOS) field effect transistor (FET) or MOSFET.
Over the past decades, the MOSFET has continually been scaled down in size and modern integrated circuits are incorporating MOSFETs with channel lengths of less than 0.1 micron. Devices with a 65 nm feature size (with the channel being even shorter) are currently in production. The decrease in feature size has resulted in certain challenges because small MOSFETs exhibit higher leakage currents, and lower output resistance than larger devices. Still, smaller MOSFETs are desirable for several reasons. The main reason to make transistors smaller is to pack more and more devices in a given chip area, reducing the price per chip. Additionally, the reduction in transistor dimension can help increase the speed.
Because of small MOSFET geometries, the voltage that can be applied to the gate must be reduced to maintain reliability. To maintain performance, the threshold voltage of the MOSFET has to be reduced as well. As threshold voltage is reduced, the transistor cannot be switched from complete turn-off to complete turn-on with the limited voltage swing available. Subthreshold leakage, which was ignored in the past, now can have a significant impact on device performance.
A gate electrode is part of an integrated circuit. For example, a CMOS transistor comprises a gate structure disposed between source and drain regions that are formed in the semiconductor substrate. The gate structure generally comprises a gate electrode and a gate dielectric. The gate electrode is disposed over the gate dielectric to control a flow of charge carriers in a channel region that is formed between drain and source regions beneath the gate dielectric. The gate dielectric typically comprises a thin material layer having a dielectric constant of about 4.0 or greater (for example, gate oxides such as silicon dioxide (SiO2), silicon oxynitride (SiON), and the like).
The gate oxide, which serves as insulator between the gate and channel, should be made as thin as possible to increase the channel conductivity and performance when the transistor is on and to reduce subthreshold leakage when the transistor is off. However, with current gate oxides with a thickness of around 1.2 nm (which in silicon is ˜5 atoms thick) the quantum mechanical phenomenon of electron tunneling occurs between the gate and channel, leading to increased power consumption.
It is often traditional transistors, which are often planar, which may experience the aforementioned current leaks. Thus, as transistors become smaller, current leaks through them, which increases as the transistor size decreases. A possible solution to this problem is a three-dimensional gate structure. In these gates, the channel, source and drain are raised out of the substrate and the gate is then draped over the channel on three sides. The goal is to constrain the current to only the raised channel, and abolish any path through which electrons may leak. One such type of transistor is known as FinFET, in which the channel connecting the source and drain is a thin, “fin” jutting out of the substrate. This results in the current being constrained to only the now raised channel, thereby preventing electrons from leaking. These gates are often termed multi-gate. An example of such a multi-gate trasnsitor design is the FinFET, in which the channel connecting the source and drain is a thin “fin” extending from the silicon substrate.
However, while current leaks are prevented, there is a different challenge where a 3-D structure is used, because it is necessary to deposit work function material extremely conformally. Despite the promise that these multi-gates structures show, there are difficulties because the three-dimensional nature of the gates requires that the work function metal be highly conformally deposited. Current methods utilize physical vapor deposition (PVD) techniques for work function metal, which makes it exceedingly difficult to deposit the thin, conformal films that are needed. Thus, there is a need for improved methods for forming metal gates, particularly in the field of mutli-gate structures.